(1) Field of the Invention
The present invention relates to integrated circuits on semiconductor substrates, and more particularly to a simplified process for fabricating unified stacked contacts on static random access memory (SRAM) cells having polysilicon load resistor.
(2) Description of the Prior Art
Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) circuits are used extensively in the electronics industry for storing data in digital systems, such as computers. The SRAM is much faster than the DRAM circuit, but is more costly to manufacture. However, because of its speed the SRAM is ideal for use as a cache or buffer memory to speed up the system performance, and is therefore preferred over the DRAM device. Each of the memory cells on a SRAM device is usually composed of six transistors and functions as a static latch or flip flop circuit, and does not require a refreshed cycle like a DRAM cell. Unfortunately, the SRAM devices require more processing steps than the DRAM and is therefore less cost effective to manufacture. Typically, the two load transistors in a six-transistor CMOS SRAM cell are composed of P-channel thin film field effect transistor (TFT) that require additional processing steps. One alternative SRAM device manufactured in the semiconductor industry is one in which the thin film transistor (TFT) are replaced by polysilicon load resistors. This simplifies the processing by avoiding the need to fabricate a TFT, but is still less cost effective to make than the DRAM cell, and there is still a strong need in the industry to simplify the process.
Another concern with the conventional TFT SRAM cell is the non-ohmic stacked contacts that are formed in the contact openings, and occur at interfaces between polysilicon layers having different types of conductive dopants (P.sup.+ /N.sup.+). The polysilicon load resistor SRAM cells avoid the unwanted occurrence of these P.sup.+ /N.sup.+ junctions.
A circuit schematic for a typical polysilicon load resistor SRAM cell, commonly referred to as poly-load SRAM, is shown in FIG. 1. Only one of the cells in the array of cells is shown in FIG. 1. The SRAM circuit is fabricated using polysilicon resistors that are doped with an N-type conductive dopant for the load resistors, labeled P1 and P2 in FIG. 1. Two N-channel FETs formed in and on the substrate are used for the driver transistors, labeled N1 and N2, and two N-channel FETs, formed at the same time, are also used as the pass transistors, and labeled WN1 and WN2 in FIG. 1.
Briefly, the SRAM circuit functions as follows. Address row and column decoder circuits on the periphery of the SRAM chip (not shown) select a memory cell. Referring to FIG. 1, the applied gate voltage on the word line WL switch on the pass transistors WN1 and WN2. The voltage at the nodes Q1 and Q2 between the load resistor P1 and drive transistor N1 and between P2, N2, respectively are sensed on the bit lines BL1 and BL2 during the read cycle to determine the state of the SRAM latch. During the write cycle when the write circuit (not shown) is enabled an impressed voltage on the bit lines can switch the voltage levels on the latch and thereby can switch the state of the cell that stored the binary data representing the one's and zero's.
Typically, during the fabrication of the SRAM circuit on a semiconductor substrate several layers of patterned conductivity doped amorphous or polysilicon films are used to form parts of the N-channel transistors, the polysilicon resistors and the intralevel connections. The polysilicon layers are separated and electrically insulated from each other by dielectric layers, such as silicon oxide. These various electrically conducting polysilicon layers and portions of the substrate are then interconnected by forming contact openings in the insulating layers between the various polysilicon layers, such as by photoresist masking and etching. Typically, the conventional SRAM cell requires a large number of masking and etching steps that include the patterning of about three polysilicon layers and about three masking and etching steps to form the contact openings between the polysilicon layers and to the substrate. It is also necessary, in the conventional process, to deposit the first polysilicon layer in two steps (split polysilicon deposition) to form the pass and driver transistors, thereby further increasing the number of process steps. Therefore, there is a very strong need in the semiconductor industry to reduce the number of processing steps.
One methods have been described by T. Okazawa, U.S. Pat. No. 4,980,732, for improving the SRAM-Thin Film Transistor (TFT) and for forming metal plug contacts to the substrate. Okazawa addresses a method for making TFTs with lower off currents by off setting the drain side of the FET channel and in the prior art of the same patent there is described the use of aluminium to form an ohmic contact between the P doped drain of the P-channel TFT and source of the N-channel FET formed on the substrate. However, the method dose not address the fabrication of poly-load SRAM nor methods of reducing the number of processing steps.
Therefore, there is still a strong need in the semiconductor industry for methods that reduce the number of masking levels and number of processing steps, and thereby improve the SRAM structure and provide a more cost effective SRAM process.